IBM Reports Advance in Shrinking Chip Circuitry

Earlier this month IBM announced that they “have created a “test” chip with transistors 7 nanometers thick.” See the full story HERE

This direction is consistent with the ESD Association’s ( white paper Electrostatic Discharge (ESD) Technology Roadmap – Revised March 2013 which forecasts increased ESD sensitivities stating:

“Also, RF circuit operations will continue to become more prevalent while these pins can tolerate very low capacitive load from ESD cells. Due to these trends, the ICs are expected to become even more sensitive to ESD events in the years 2012 and beyond. Therefore, the prevailing trend will be circuit performance at the expense of ESD protection levels.”

This continuing trend is moving most components used in electronics to Class 0 levels:

0A < 125V
0B 125 to < 250V

The increased sensitivity is encouraging manufactures to increase ESD protective redundancies by:

– Controlling access to the ESD Protected Area
– Adding ESD control items to the ESD control plan
– Continually monitoring the performance of the ESD control items with data acquisition software.
– Increasing the frequency of periodic compliance verification measurements.

For more information on improving an ESD Control Plan see the InCompliance article – Now is the Time for ESD Control Programs to be Improved

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